Performance Evaluation of Hardware Trojan in SoC with Custom Overlay

The advancements in development of hardware design and implementation for manufacturing of Integrated Circuits (IC) has grown manifold in recent time. With these equal challenges have grown from different stake holders of these process. It utilizes VLSI design and technology processes for development and the steps involved make it vulnerable to malicious modification of the hardware or circuit is popularly known as Hardware Trojan (HT). To tackle the security and confidentiality of such circuits is very crucial during the development and implementation for reliable operation in the field. The modifications and improvements in the hardware Trojan making it difficult to detect and mitigate its effect. Different researchers have taken this challenge and provided numerous solutions and are in process of continuous improvement. This paper provides the different level of implementation of Hardware Trojan insertion in the System on Chip and the analysis is presented for it using different assessment characteristics. The first implementation of hardware Trojan as AES Cipher logic block connected to embedded softcore processor Microblaze running on FPGA is carried out using development kit. The device utilization and other parameters compared to analyze the implementation and its effects. The second implementation of Hardware Trojan is done using Basic Custom IP core connected to ARM9 processing unit present on the FPGA. The Xilinx Linux operating system running and the Python programming is used to run and trigger the Hardware Trojan using Overlay package. The device utilization and other parameters are compared to analyze the implementation and its effects.