Design of a 12-bit Segmented Current-Steering DAC

A current-steering digital-to-analog converter (DAC) is a commonly used type of DAC in digital signal processing and communication systems. In this design, a 12-bit DAC with a sampling rate of 200 MS/s was implemented using TSMC
$\mathbf{0.18}\ \boldsymbol{\mu} \mathbf{m}$
CMOS technology. To improve the overall performance of the DAC, a segmented current-steering architecture was used with a 5+3+4 configuration. The highest 5 bits are encoded with a thermometer code, the middle 3 bits are encoded with another thermometer code, and the lowest 4 bits are encoded with a binary code. The circuit layout was optimized using a random walk layout method, and the results show that the integral nonlinearity (INL) and differential nonlinearity (DNL) were also improved.