Stress-Strain Model in Plated Through-Holes of Multilayer Printed Circuit Boards

As a critical component of printed circuit boards, the plated through-hole has become the key factor in the reliability issues of printed boards. Existing plated through-hole stress-strain models often simplify the plated through-hole as a one-dimensional structure and overlook factors related to the multi-layer board structure and external pads. In this paper, building upon existing models, we consider the multi-layer board through-hole structure and factors affecting its stress-strain distribution to establish a reasonable plated through-hole stress-strain model. This model rapidly assesses plated through-hole lifetimes on multilayer printed circuit boards. The rationality and accuracy of the model were validated and refined using finite element analysis results, which aligned the model more closely with engineering conditions.