RISC-V Hardware Debugging System Design for Embedded Microprocessors

A hardware debugging system based on the RISC-V debugging protocol is designed and implemented to meet the debugging needs of a RISC-V microprocessor applied in an embedded scenario. The system can complete the functions of program download, breakpoint debugging, single-step debugging, etc. Aiming at the hardware resource limitations in embedded scenarios, the system designs a two-wire debugging interface and implements the port multiplexing function, which saves the pin hardware resources. The simulation verification environment and FPGA prototype verification environment were built to test the basic debugging functions, and the results show that the hardware debugging system can meet the debugging requirements.