Non-wet Simulation and risk prediction of 2.5D Package

As one of the most popular multi-chip integration technologies, 2.5D package is of great significance in applications such as artificial intelligence, cloud computing, big data, etc. In these applications, high speed, high bandwidth and interconnect density are in highly demand. However, the increasing of integrated chips quantity in 2.5D package usually leads to warpage problem, which gives rise to obvious gap between 2.5D module and substrate. The non-wet risk in flip chip (FC) process grows with the mismatch in flip chip area (FCA) between 2.5D module and substrate. In this paper, the FC process of assembling 2.5D module onto the substrate is simulated by finite element method (FEM) to study the solder bump non-wet behavior, which is introduced by the warpage of substrate and 2.5D module. Based on the analysis of warpage matching, the effects of molding thickness and molding material are respectively studied. Particularly, the trace mapping technique is in use to refine the metal layers model in substrate. The results show that, lower molding thickness and lower molding material coefficient of thermal expansion (CTE) can decrease the solder bump non-wet risk. The findings will widen the understanding of FC non-wet behavior and provide suggestion for optimizing 2.5D package design.