Study on the Key Technology in FC-SiP Packaging with 4L ETS Substrate

The challenge and optimization of strip level warpage of a system in package(SiP) with 4L ETS substrate are presented. Comparing with conventional substrate, ETS substrate has finer trace space and higher I/O, but also brings strip level warpage risk due to the elimination of rigid core materials. This SiP contains one bottom flip chip die and two stacked memory dies, forming a three-layer stacking structure. we showed the detailed warpage behavior of the SiP during assembly process. The results show that this complex structure exacerbates the bending degree, bringing many challenges during the assembly process. This bad warpage behavior tends to induce not only workability issues, like affecting the automatic mass production capability, but also lead to many package failures, such as non-wet and bump/ELK crack. Finally, we discussed the factors affecting strip level warpage behavior and find out some methods to improve the above problems, from substrate design, material selection to tooling modification. In addition, this article establishes a strip warpage simulation model with flip chip die attached on substrate after reflow.