I. Introduction
The conventional wafer level packaging involves arranging the I/O pins of a chip in an area array bump using the Fan-In technology, known as Fan-In WLP, shown in Fig. 1. However, with the progress of semiconductor technology nodes, Fan-In WLP currently faces significant challenges. The chip size continues to shrink, and the higher-performance chips require more and more I/O pins, the chip area will not be able to accommodate enough solder balls. The Fan-out packaging extends the routing and interconnecting through the ultrathin redistribution layers (RDLs), shown in Fig. 2. It is suitable for mobile systems because of its low structure profile, compact in size, high I/O density, and good thermal performance [1].