A stress evaluation approach for the silicon with nano-TSVs by Raman spectroscopy

Nano-TSV (Through Silicon Via) is a three-dimensional integrated vertical interconnect technology to increase the interconnect density, to improve chip performances with reducing chip power consumption. As the array of Nano- TSVs is much closer to the functional area of the chip, the thermal stress is critical to the transistors on the silicon surface due to the coefficient of thermal expansion (CTE) mismatch between the silicon and the copper filled in nano-TSV. In this study, we present a new method for stress evaluation of the silicon with nano-TSVs using Raman microscopy. Taking the advantages of dimensionless analysis and similarity criterion, the method estimates the stress variation in the small silicon region with nano-TSVs by the testing results from the micro- TSVs by Raman microscopies. The results help to put forward solutions to reduce stress and improve the reliability of advanced 3D integration.