Warpage Estimation of Panel-Level Packaging by AI-assisted Design on Simulation

The area utilization rate for fan-out panel level packaging (PLP) is higher than rounded Wafer Level Packaging (WLP). This is due to the fact that both the chip and the carrier in PLP are square-shaped. The mass production characteristics of PLP provide low manufacturing costs, and PLP becomes a potential technology. However, due to the large footprint of PLP, the warpage problem PLP can be more severe than those in WLP. Technically, excessive warpage can lead to alignment challenges, potentially causing a drop in production yield. This makes the investigation of PLP’s warpage issue critically important. Two major reasons cause the warpage problem, the mismatch in the Coefficient of Thermal Expansion (CTE) between materials and the shrinkage of the epoxy molding compound during its curing process.To investigate the warpage problem, this study employs a design on simulation approach, utilizing the finite element method (FEM) for simulations, in which a viscoelastic model is used to simulate the molding layer to present the real situation of EMC. Process modeling technology is applied to approach actual PLP production conditions. Furthermore, this study also applies an AI algorithm to our methodology. That is, AI-assisted design on simulation. The process is to train the AI model by establishing FEM warpage results obtained under different feature sizes. And when future PLP data becomes available, it can further shorten the time required to estimate the warpage mode after the delamination process.