Logic locking emulator on FPGA: A conceptual view

Hardware designs must be protected from unauthorised access and intellectual property theft using logic locking approaches. In this work, a novel conceptual view and architecture of an FPGA-based emulator are presented. This emulator is specifically made to make it easier to create and test unique logic locking mechanisms for hardware designs. Researchers and designers can experiment with different locking strategies on the emulator’s versatile and effective platform, which allows for modification based on particular design requirements and security goals. Moreover, the paper presents the creation of test patterns for assessing the logic locking’s security. Comprehensive test patterns can be developed by utilising the emulator’s capabilities in order to replicate various attack scenarios and evaluate the robustness of the locking techniques against various attackers. Researchers can enhance the subject of hardware security and safeguard designs against potential vulnerabilities by using the emulator architecture in conjunction with the creation of test patterns. The emulator architecture will need to be improved, test pattern creation will need to be optimised, and advanced machine learning methods will need to be used to improve security evaluations.