Use of current-mode and voltage-mode receivers together for on-chip multipoint-to-multipoint data transmission across global interconnects

In this paper, a mix of current-mode and voltage-mode receivers in hybrid-mode multipoint-to-multipoint signaling architectures for on-chip data transmission over global interconnects has been discussed. In multi-processor system-on-chips (MPSoCs), at any instant of data sharing among multiple cores, one of the cores acts as the transmitter while others act as receivers, therefore resulting in multi-receiver architecture. Hybrid signaling architectures are a combination of both VM and CM receivers and recent works of literature have proposed energy-efficient hybrid-mode multipoint-to-multipoint signaling architectures for high-speed on-chip data transmission over lossy interconnects by utilizing CMRx termination with intermediate VMRxs, however, there are trade-offs associated with the current-mode and voltage-mode signaling scheme. Therefore in this paper, variation in the number of CM and VM receivers has been analyzed for determining the optimal combination of receivers in hybrid signaling architectures for on-chip data transmission.