Contents I. Introduction
The size of a DRAM cell must be reduced due to the steadily rising demand for high-speed and dense memory [1–8]. The most significant problem with DRAM scaling is reducing the capacitor size since it decreases the charge storage [1–13]. This negatively impacts charge retention, which calls for frequent refresh cycles [3–6]. Data is stored in the capacitor as an electrical charge in a standard DRAM cell, but the charge leaks away with time. To maintain the stored data, DRAM must be refreshed frequently. Refresh has a detrimental effect on power consumption and DRAM performance [4]. Performance and power overheads dramatically rise as DRAM device speed rises with each new technology [3–8]. Moreover, increased leakage current is brought on by transistor scaling. In this work, we use a potential well to store charge instead of a capacitor, making the DRAM scalable. Further, we introduce electrostatic barriers in the device, which inhibit charge leakage and increase the retention time by . Thus, the proposed device can work with refresh cycles of lower frequency and save power dissipated in a circuit.
