An Efficient Multiplier Architecture using Improved Full Adder Circuit

The propose works shows an efficient multiplier architecture using improved full adder digital logic. The propose architecture is the workhorse in designing in digital signal processing (DSP) system, which enable to perform complex mathematical operations with improved efficiency and accuracy also improved in the field of area, power, delay etc. In this work, a modified improved full adder circuit to design multiplier circuit which improves circuit performance in terms of power and delay. In Improved full adder approx 30% of power decreased than Conventional Full adder circuit and in modified Multiplier approx 26% of power decreased than Normal Multiplier Circuit. Xilinx Vivado 2020.1 simulation software is used for designing multiplier circuit.