Adaptive Reconfigurable LFSR: Dynamic Tapping and Reseeding for Enhanced Pseudo Random Number Generation

The paper presents a reconfigurable Linear Feedback Shift Register (LFSR) that has the capacity to reseed and is composed of a seed generator circuit which is a 4-bit LFSR. The size of the pseudorandom pattern generator is 64 bit. The 4-bit LFSR functions as both the seed generator and selector of the feedback path for the 64-bit LFSR. The inputs of the circuit are clock, reset, select lines (s), and seed. After the reset initializes the LFSR the select lines (s) determines the mode of the LFSR i.e., internal (s=0) or external (s=1). The circuit yields a 64-bit output, with tap points dynamically chosen based on the 4-bit LFSR output, increasing the randomness of generated patterns. The design offers enhanced control over pseudo-random number generation through reseeding and configurable taps. The simulation software used is Xilinx Vivado 2020.1 and the design is implemented in Verilog.