Unveiling the Role of Hole Barrier Traps on ON-Resistance Instability after Gate Bias Stress in p-GaN Power HEMTs

Gate bias effects on p-GaN power HEMTs stability are primarily investigated in terms of threshold voltage (V
T
) drifts. However, applying positive and negative gate bias for long time can also induce ON-resistance (R
ON
) instability which is often overlooked in the literature. In this work, we characterize I
D
-V
GS
after applying a –6/+6 V gate initialization (VGP) bias for 3000 s at different temperatures and reproduce the same characteristics by means of numerical simulations. The comparison between measurements and simulations allowed attributing the observed R
ON
dispersion to barrier acceptor traps emitting/capturing holes (injected/removed by the Schottky contact on the p-GaN layer) after V
GP
= –6/+6 V, respectively. Characterization of I
D
/R
ON
transients at different temperatures obtained after initialization at +6 V while keeping a gate baseline bias V
GB
= –6 V allows extracting an activation energy E
A
≈ 0.4 eV. This feature is also reproduced by the simulations, further indicating that the underlying mechanism of R
ON
increase is the charge of acceptor traps in the barrier mediated by hole removal through the Schottky gate contact on the p-GaN region.