Parallelization of the Shift and Add Reducer

This paper discusses a novel method for parallelization of a Shift and Add Reducer. This improvement allows for high levels of parallelization and decreases the number of cycles required for each calculation significantly. This improvement has little impact on performance characteristics other than simply decreasing the number of cycles required for an operation. Results show that while the area and critical path characteristics of the design remain unaffected at different levels of parallelization the number of cycles required for an operation decreases signficantly. This change results in a more efficient architecture that is very competitive with others in the field of modular reduction hardware.