Unlocking the Potential of LDPC Decoders with PiM Acceleration

This paper introduces a novel concept for exploiting processing in-memory (PiM) hardware decoding low-density parity-check (LDPC) codes. The PiM hardware can be used to mitigate the high cost of data movement in modern computing systems by placing computing units near memory where data resides. The memory hierarchy and the parallel nature of the limited arithmetic units allow the multithreaded-based paral-lelization of the LDPC decoder inside each data processing unit (DPU) and the simultaneous launch of multiple LDPC decoders. The experiments confirm a speedup of 1155 ×, compared to the baseline, a sequential high-end CPU, for the binary LDPC decoder of CCSDS-231 standard reaching 742 Mbps of global throughput performance in-memory.