A Fixed-Point Pre-Processing Hardware Architecture Design for Complex Independent Component Analysis

Complex Independent Component Analysis (c-ICA) is widely employed in many applications involving MIMO communication systems, radar signal processing, medical imaging (MRI), and other fields where data is represented in complex number format. This paper proposes a configurable fixed-point pre-processing hardware accelerator for c-ICA algorithm that offers a balanced combination of high throughput with low area and power costs. The proposed accelerator performs the c-ICA pre-processing in multiple stages including a step for centering and covariance matrix computation, followed by eigenvalue decomposition (EVD) and whitening matrix computation units. The datapath flow is pipelined in such a way that each stage in the path is operated in parallel and individual stage designs are pipelined within, resulting in high throughput. The paper characterizes the proposed architecture design using 45 nm process flow and compares its performance with the current state-of-the-art (SOTA) designs. Experimental results showcase substantial savings in processing time and computational resources, making it highly suitable for real-time and resource-constrained applications. A throughput gain of 49.96% and complexity reduction of 22.23% and 19.63% for covariance cum centering and EVD units respectively was achieved by the proposed design over the best of the SOTA designs. The hardware design files are made freely available for further usage to the designers and researchers’ community [1].