Modeling of Tamper Resistance to Electromagnetic Side-channel Attacks on Voltage-scaled Circuits

The threat of information leakage by Side-Channel Attacks (SCAs) using ElectroMagnetic (EM) leakage is becoming more and more prominent for crypto circuits. This paper models tamper resistance to EM SCAs on voltage-scaled crypto circuits. It is well known that if the supply voltage is donwscaled, attackers need to acquire more EM traces to extract secret key information in crypto circuits. Therefore, crypto circuits can process more data safely. However, their supply voltage dependence is not fully studied. This paper thus firstly models voltage dependence of the strength in the EM emission from crypto circuits. Then, this paper proposes the tamper resistance model which analytically expresses the relationship between the supply voltage and the minimum traces to disclosure based on test vector leakage assessment. This helps consider to optimize the trade-off relationship between encryption performance and tamper resistance to the information leakage. The proposed models are validated by measurement results using an Advanced Encryption Standard (AES) circuit with a 180-nm process technology.