Transduction Method for AIG Minimization

Due to the recent hike in the cost of silicon wafers, area minimization is becoming increasingly important, which makes high-effort circuit optimization more attractive, despite the additional runtime. In this paper, we revisit the transduction method originally proposed in 1980’s. The method computes don’t-cares for nodes in the circuit and iteratively performs wire reduction and other transformations. Several novel variations of the transduction method are proposed, aiming at high-effort area minimization for and-inverter graphs (AIGs) with up to one thousand nodes. These variations are applied iteratively by a script, which also performs stochastic optimization with randomized parameters. The script has been used to minimize AIGs derived from the truth tables provided at IWLS 2022 Programming Contest. In all cases, the resulting AIG sizes are the same or smaller, compared to the best results produced by the contest participants.