Deep Learning for Fault Detection of Digital VLSI Circuits

With the increasing complexity and scale of digital VLSI designs, ensuring reliability in IC design necessitates effective fault detection processes during the pre-silicon stage. Many fault detection algorithms lead to significant computational time due to the problem of search space explosion. To handle the ever-growing volume of data, deep learning algorithms, a subset of machine learning techniques, can be employed. In this paper, we propose two novel approaches for fault detection (FD) of digital VLSI circuits, specifically targeting stuck-at faults. The first proposed model is semi-supervised FD model that aims to mitigate the search space explosion issue by leveraging both unsupervised and supervised learning processes. The second presented model is based on an optimizer for finding the appropriate configurations for detecting stuck-at faults in digital circuits. The initial proposed model achieves maximum validation accuracy of approximately 98% applied to circuits from ISCAS’85. This model yields a higher accuracy compared to the second approach that achieves maximum accuracy of around 95% when applied to the same circuits from the ISCAS'85 benchmark.