Signal & Power Integrity Analysis and Solutions for HBM Gen3

The growing requirements for High Performance Computing (HPC) applications designed to support Artificial Intelligence/Machine Learning (AI/ML) workloads has catapulted the demand for the High Bandwidth Memory (HBM) DRAM devices. Designing the HBM Gen 3 IOs is challenging due to a variety of factors including but not limited to area, power, and performance. The challenges specific to HBM3 Signal and Power Integrity pertain to optimizing the Power Delivery Network (PDN) to ensure the noise specification are met and signal path optimization to minimize losses and crosstalk. Determining the PDN target impedance to meet the noise specification and hence the Power Supply Induced Jitter (PSIJ) is key challenges which impacts the overall system performance. Here in this paper, we propose the simulation methodology to capture the worst-case behavior, optimize the design and minimize the simulation effort required to successfully sign-off the HBM3 interface. The simulation approach has been identified to be slightly conservative when correlated with the silicon measured date giving us good confidence on the methodology and thus providing solutions to evolve for next generation HBMs.