Advanced Acceleration and Implementation of Convolutional Neural Networks on FPGAs

In recent years, embedded platforms became attractive targets to deploy machine learning (ML) -empowered control and processing systems. However, securing a high performance executability to satisfy the hard real-time constraints of such systems on resource-limited platforms, such as FPGAs, is a challenging task. This paper introduces a methodology for deploying hardware-accelerated, adaptable convolutional neural networks (CNN) on embedded FPGA platforms. It enables automated synthesis of hardware IPs, instantiation of CNN architectures and mapping of the CNN layers processing to hardware IPs. This will result in iteration-free deployment reducing the expensive cost of HW synthesis, so that the acceleration hardware IPs are synthesized once and configured at runtime following the CNN architecture. To demonstrate the applicability and assess the performance of our deployment model, we implemented and deployed a segment-based acceleration of a image classification CNN on Xilinx ZYBO Z7 FPGA board. Among others, we have analyzed the computation performance, accuracy and trade-offs between CNN size, image segmentation size, resources utilization and scalability.