Signal integrity aspect of High Speed Interface Routing in multilayered PCB environment

The strategy of selecting the routing layer to attain better signal quality of high-speed channel interfaces is presented. The effective capacitance and inductance associated with the overall trace will get modified especially depending on uses of transition. Moreover, most of the HSIO interfaces routing possess upper limit on the number of transitions vias without stressing on the selection of trace routing layer and its connection with transition via. However, the analysis carried out shows that the optimized trace routing layer assignment helps to mitigate the effective via parasitic that helps to attain better channel loss margin. Therefore, a systematic numerical analysis is presented to develop the more useful consideration regarding the routing of HSIO interface (USB4 @10Gbps) corresponding to multilayer PCB. A commercially available 3D field solver is used to analyze the frequency domain channel response corresponding to USB4 interface. The time domain analysis is also carried out to compare the parameter of eye diagram. It is shown that routing of HSIO in appropriate signal layers helps to provide better margin. For the USB4 interface, an improvement of $3.6 \mathrm{~dB}$ in insertion loss and 49mV improvement in eye height is recorded that helps to meet the Retimer specification.