ASIC Design and Implementation of a Power-Delay Product Optimized Arithmetic Operational Unit

The architectural design of a 16-bit arithmetic operational unit that has an optimized power-delay product is introduced using the technique of iterative carry-save addition and error-tolerant addition. The incorporation of Low-Power Selector Based Error-Tolerant Adders in the design and implementation of the iterative carry-save adder and multiplier enhances the speed and lowers the power consumption. The proposed arithmetic operational unit is modelled using Verilog hardware description language. The ASIC implementation and synthesis is performed using Cadence Genus tool with 45 and 90 nm gpdk standard technology libraries. A considerable reduction was noticed in the power, delay, and PDP of the proposed arithmetic operational unit.