Chip-Package Interaction: A Case Study Applied To A Mature Technology Node

Chip Package Interaction (CPI) is a major reliability concern in the semiconductor industry. This concern had been mainly addressed in advanced technology nodes like 28nm and below [1],[2],[3]. Here mainly, the introduction of mechanically weaker ultra-low-k Interlayer Dielectric (ILD) materials in the back end of line (BEOL) has significantly enhanced the risk for CPI related failure mode. However even in a mature technology node, a thorough CPI assessment needs to be carried out, since numerous factors impact the CPI performance.This paper reveals in a case study the applied methodology by GlobalFoundries for a CPI assessment. Based on modelling and experimental data generated on wafer and package level, an explicit recommendation is made for the design of the silicon with respect to the aluminum bond pad thickness and the presence of an organic passivation layer in a flip-chip package configuration.