Assembly process characterization of 3D Stacking of Heterogeneous Chiplets

The demands of advanced electronics products such as Automotive Radar and High functionality Smartphones have driven the growth of RF packaging market especially in radio frequency (RF) applications. Hence there is a need for RF devices with smaller form factors and higher speed operation. In this work, we have successfully demonstrated an assembly approach of CMOS and RF device chiplets stacked in a 3D configuration on a modified FOWLP platform. The chip-to-wafer bonding and different assembly processes will be discussed in the paper. The TSV measurement results and the daisy chain measurement results will also be updated.