A Probabilistic Model for Estimating Defect-Limited Yield of ASICs

This paper summarizes 15 statistical yield models for estimating the defect-limited yield of Application-Specific Integrated Circuits (ASICs). Probabilistic modelling approaches were used to adjust for process nodes (PAF) and design complexity (DAF). An Excel-based calculator with 15 models was developed. Yield was estimated per ASIC, also per 5 circuit types in an ASIC, which include IO, Logic, Memory, Pure Analog, and High-speed Digital. The output yield values were adjusted based on design complexity and process nodes. Design adjustment factor (DAF) and process adjustment factor (PAF) were estimated and used as multipliers to adjust yield values. Three Bayesian networks were developed to show yield dependencies on design influencing factors, while a
$2\mathrm{D}$
geometry model was constructed to simulate the yield due to particle landing at different technology nodes. The estimated results were validated by manufacturing test data from sort and final tests of 4 different ASICs. Estimated results for each case matched the actual with reasonable percentage of difference.