Efficient ML-Based Performance Estimation Approach Across Different Microarchitectures for RISC-V Processors

High-level performance estimation using Machine Learning (ML) can significantly facilitate the exploration of a wide range of processor microarchitecture solutions at the early stage. Moreover, for the selected microarchitecture, it can remarkably accelerate the software optimization step. Recently, ML has been successfully applied to estimate performance, in particular the clock cycles, for various microarchitecture implementations. However, this is clearly not sufficient as the modern processor microarchitectures are complex and require deeper insights into microarchitectural behaviors for better high performance estimation. In this context, finding an accurate and fast approach that can support performance estimation of various microarchitecture implementations of RISC-V Instruction Set Architecture (ISA) is very challenging. In this paper, we go beyond performance estimation based on clock cycles, i.e., we expand on ML techniques to estimate microarchitectural behaviors. We propose a novel approach based on ML to estimate the performance of embedded software on RISC-V processors across different microarchitectures. Our approach leverages a fast functional simulator, cycle-accurate Register Transfer Level (RTL) implementations, and ML techniques to generate Predictive Models (PMs) that provide accurate performance estimation while maintaining fast simulation time. In addition to measuring the clock cycles, we also provide insights into the microarchitectural behavior of different microarchitectures by estimating cache misses/hits, branch prediction behavior, and memory dependencies. Experimental results on four real-world cycle-accurate implementations of RISC-V ISA with different microarchitectures at RTL show that using the proposed approach leads to a huge performance boost up to
$\mathbf{2261.4}\times$
compared to RTL simulations with an average prediction error 0.4%.