Sampling PLLs (SPLLs) are currently the most popular architecture for generating ultralow-jitter signals due to their high-gain sampling phase detectors (SPDs) that can significantly reduce in-band phase noise (PN). However, to maintain this advantage even in the fractional mode, SPLLs must remove the quantization error (Q-error) of the very precisely. The use of a digital-to-time converter (DTC) before the SPD [1] (top left of Fig. 10.5.1) is a common solution, but the inherent non-linearity of the DTC, i.e., , introduces fractional spurs and the leakage of the Q-error, which increases the inband PN. There are two approaches that are used widely to reduce . The first approach (①) is to use a typical DTC and then compensate for using a digital pre-distortion (DPD) that modifies the accumulated code, i.e., , to have the inverse function of . However, this technique requires significant design resources (in terms of power and area) to achieve high accuracy. The second approach (②) is to design a linear DTC with an inherently small . The constant-slope DTCs (CS-DTCs) reduced by charging a capacitor with the same ramp rate regardless of the initial voltage determined by . The inverse constant-slope DTC (ICS-DTC) [3] further reduced by generating the initial voltage by controlling the precharging time as a multiple of the VCO period , i.e., is an integer), to remove the voltage dependence of the capacitor and the current. However, the downside is that a longer precharge time (or is required to achieve the higher DTC resolution, which increases the thermal noise of the DTC and hence the in-band PN.
Abstract:
Sampling PLLs (SPLLs) are currently the most popular architecture for generating ultralow-jitter signals due to their high-gain sampling phase detectors (SPDs) that can s...Show MoreMetadata
Abstract:
Sampling PLLs (SPLLs) are currently the most popular architecture for generating ultralow-jitter signals due to their high-gain sampling phase detectors (SPDs) that can significantly reduce in-band phase noise (PN). However, to maintain this advantage even in the fractional- N mode, SPLLs must remove the quantization error (Q-error) of the \Delta \Sigma \mathrm{M} very precisely. The use of a digital-to-time converter (DTC) before the SPD [1] (top left of Fig. 10.5.1) is a common solution, but the inherent non-linearity (NL) of the DTC, i.e., NL _{\mathrm{DTC}}, introduces fractional spurs and the leakage of the Q-error, which increases the inband PN. There are two approaches that are used widely to reduce NL _{\mathrm{DTC}}. The first approach (①) is to use a typical DTC and then compensate for NL _{\mathrm{DTC}} using a digital pre-distortion (DPD) that modifies the accumulated \Delta \Sigma \mathrm{M} code, i.e., D_{\mathrm{AQ}}, to have the inverse function of NL _{\mathrm{DTC}} [2]. However, this technique requires significant design resources (in terms of power and area) to achieve high accuracy. The second approach (②) is to design a linear DTC with an inherently small NL _{\mathrm{DTC}}. The constant-slope DTCs (CS-DTCs) reduced NL _{\mathrm{DTC}} by charging a capacitor with the same ramp rate regardless of the initial voltage determined by D_{\mathrm{AQ}}. The inverse constant-slope DTC (ICS-DTC) [3] further reduced NL _{\mathrm{DTC}} by generating the initial voltage by controlling the precharging time as a multiple of the VCO period (T_{\mathrm{VCO}}), i.e., k\cdot T_{\mathrm{VCO}} (k is an integer), to remove the voltage dependence of the capacitor and the current. However, the downside is that a longer precharge time (or k\cdot T_{\mathrm{VCO}}) is required to achieve the higher DTC resolution, which increases the thermal noise of the DTC and hence the in-band PN.
Date of Conference: 18-22 February 2024
Date Added to IEEE Xplore: 13 March 2024
ISBN Information: