8.9 A 96.5% Peak Efficiency Duty-Independent DC-DC Step-Up Converter with Low Input-Level Voltage Stress and Mode-Adaptive Inductor Current Reduction

DC-DC step-up converters have been widely utilized to efficiently convert a low input voltage $(V_{IN})$ to a higher output voltage $(V_{OUT})$ in USB- or battery-powered mobile systems, including battery chargers (10 to 13V), OLED drivers (5 to 13V), etc. The conventional boost converter (CBC) needs the use of high-voltage (HV) devices such as LDMOS to withstand its high V
OUT
. Typically, HV devices have larger active area and parasitic capacitance compared to low-voltage (LV) devices with the same on-resistance $(R_{ON})$, resulting in the increase of switching loss (i.e., lower switching performance). Moreover, as the duty $(D)$ increases for higher V
OUT
in a fixed conversion ratio (CR$=V_{OUT}/ V_{IN})$, the inductor current $(I_{L})$ also increases in proportion to $1/(1-D)$ times of the load current $(I_{LOAD})$. Since a large-sized inductor with low parasitic DC resistance (DCR) is challenging to use in mobile devices due to space and cost constraints, larger I
L
causes significant conduction loss $(P_{cd,loss})$ due to DCR and limits the power efficiency in CBC [1]. To mitigate the effect of DCR in the inductor, prior works have used an additional inductor or capacitor as shown in Fig. 8.9.1 (top). A dual-path step-up converter in [2] reduces I
L
with an LC dual-path technique, which transfers the current to the output through C-path in addition to L-path, but the maximum voltage stress (MVS) across the switches is high as ${2V}_{OUT} - V_{IN}$, requiring 8V LDMOS transistors to operate with 2V input and 5V output voltages. A hybrid converter described in [3] utilizes two inductors and one capacitor for continuous current delivery to the output, reducing the current flowing through each inductor. However, the sum of two inductor currents is still high as $I_{LOAD} /(1- D)$ while HV LDMOS transistors are also required since MVS across the switches is high as V
OUT
. Another approach to decrease MVS of switches is using a 3-level boost converter in which the voltage stress across switches can be a half of V
OUT
thanks to its stacked topology. However, HV LDMOS should be still employed for the output voltage exceeding 10V, and there is no effective solution to reduce $I_{L}[4]$.