9.1 A 2mW 70.7dB SNDR 200MS/s Pipelined-SAR ADC with Continuous-Time SAR-Assisted Detect-and-Skip and Open-then-Close Correlated Level Shifting

The pipelined-SAR ADC has become popular in wide-bandwidth and high-resolution applications due to its power-efficient architecture [1]. In the pursuit of higher ADC speeds while maintaining precision and power efficiency, not only does the conversion time of the SAR sub-ADC need to be shortened, but also the speed and gain of residue amplifiers (RA) need to be enhanced. Conventional solutions to these two problems, including reducing the bit-cycling time of the SAR and increasing the RA bandwidth, often require extensive power costs, leading to a degraded power efficiency. To address the speed and gain challenges, three techniques are proposed in this work. First, a continuous-time SAR-assisted detect-and-skip (CTDAS) to parallelize the MSB conversion with ADC sampling, thus cutting down the $1^{\text{st}}$-stage sampling and conversion time by 35% when compared with a conventional detect-and-skip (DAS) technique. Second, an open-then-close correlated level shifting (OCCLS) technique applied in the residue amplifier, which significantly speeds up the first phase by open-loop amplification reusing the first two high-bandwidth stages of the RA. With the aid of a detect-and-cut loop, an optimal voltage gain in the first phase is obtained across PVT variations, thus realizing an >80dB equivalent RA open-loop gain $\left(\mathrm{A}_{\mathrm{EO}}\right)$ across PVT variations. Third, a hybrid static-floating ringamp architecture is implemented to improve the noise performance of the RA and to fit in well with the OCCLS scheme. Thanks to the techniques above, the 22nm prototype achieves 70.7dB SNDR under 200MS/s while consuming 2.0mW from a 0.9V supply. It measures a best energy efficiency of 177.7dB Schreier FoM with fs >150MS/s.