Design and Energy Dissipation Analysis of Full-Adder for Low Power Applications Using Reversible Logic Gates

Low-power architectures are gaining traction in applications ranging from IoT to quantum computing. Traditional combinational logic circuits suffer from information loss and energy waste. Reversible computing mitigates this issue by sustaining input bits in the output. Adders are vital in arithmetic and logic units, impacting processor performance. Reversibility design principles offer promising ultra-low power solutions. We propose an energy-tolerant, low-power reversible full adder with optimized energy loss, reduced ancillae, garbage outputs, and quantum cost. This advancement holds potential for quantum computing and other energy-efficient applications. The transistor count per adder circuit is also reduced compared with existing architectures that exist in the literature.