A Modified Viterbi Decoder Architecture for Hardware Efficiency

Viterbi decoders play an important role in modern wireless communication systems to decode convolutionally encoded information. Hardware design of Viterbi decoders have been explored widely with a focus on achieving low area, power and delay. In this work an attempt has been made to achieve the same by combining the methodologies available in literature for modifying the Survivor Memory Unit (SMU) and Add Compare Select (ACS) unit of a Viterbi decoder. Here, the modifications on the ACS unit using T-algorithm with pre-computation together with retiming has been combined with the modification on the SMU using the pre-trace back approach. Both of these modifications that have been reported independently in literature, have been combined in this work. The architecture incorporating the modifications in the ACS unit and SMU together leads to a design with a reduced area and power of 21.21 % and 49.1 % respectively, while at the same time increasing the maximum operating frequency by 67.7 %. A comprehensive verification environment for the unit has also been developed using system Verilog layered test bench.