Combined Substitution-Box Based AES Algorithm for Low Power and High Speed Crypto-Coder System

With the demand for efficient and secure data communication increasing rapidly, crypto-coding that integrates cryptography and error control coding has become an essential part of wireless communication systems. This work deals with the design of a high speed and low power crypto-coder that uses, an Advanced Encryption Standard (AES) with an optimized Substitution - box (S-box), and a convolution encoder and a Viterbi decoder as the error control module. This design is aimed towards addressing challenges faced in the traditional implementation of low power and high speed AES architectures. It is seen that the use of the optimized AES algorithm results in 81% and 5% reduction in the power consumed and the area occupied by the crypto-coder respectively. Also, the maximum speed of operation of the crypto-coder increases by a factor of 2.5, thus lending credibility as a low power and high speed implementation.