Topology and Improved Selective Harmonic Elimination Method for the Series-Connected T-Type Multi - Level Inverter

The T-type three-level inverter (T
²
3LI) topology has been extensively employed in various industrial applications. This article further proposes a novel series-connected T-type multi-level inverter (SCT
²
MLI), whose phase leg is formed by two series-connected T-type three-level inverter phase legs. First, the basic operating principle of the SCT
²
MLI is analyzed, and the impact mechanism of different switching states on the dc-link capacitor voltages is obtained. An improved selective harmonic elimination (ISHE) method is subsequently designed, which can simultaneously restrain the common-mode voltage (CMV) and eliminate the selective low -order harmonics, while the performance of ac output voltage is not influenced. In addition, the voltages across dc-side capacitor voltages are controlled by adopting redundant switching states. When using the proposed ISHE method, the CMV is significantly restricted in comparison with the traditional SHE method. The evaluation results prove the feasibility of the proposed method.