Digital Implementation of Depthwise Separable Convolution Network for AI Applications

Convolutional neural networks(CNN) have gained widespread popularity in the fields of computer vision and pattern recognition due to their exceptional accuracy. However, the computational demands of operating large convolutions often necessitate powerful computing platforms like a Graphical Processing Unit (GPU), making it challenging to utilize CNNs on portable devices. To address this issue, advanced CNN models such as MobileNetV2 and Xception employ Depthwise Separable Convolution(DSC) instead of Standard Traditional Convolution(STC) for embedded systems. This approach significantly reduces computations and parameters while only marginally sacrificing accuracy. This innovative model structure is particularly well-suited for implementation on Field-Programmable Gate Arrays(FPGAs). In our research paper, we propose DSc accelerator within CNNs. The design allows flexibility in adapting to FPGAs of various sizes, achieving an excellent balance between hardware resource utilization and processing speed efficiency. We have successfully implemented this using the Verilog Hardware Description Language(HDL), and We have achieved the corresponding outcomes for an image size of 256 × 256 × 3.