Low Power Approximate Divider and Square Root Circuits for Error Resilient Applications

This paper introduces a new method for designing divider and square root (SQR) circuits called the adaptive approximation approach. The approach utilizes a reduced-width approximate divider/SQR circuit and a shifter to compute the division/SQR while adaptively removing insignificant input bits. For the 2n/n divider, only 2k and k bits are selected starting from the most significant ‘1’ in the dividend and divisor, respectively, and the remaining bits are truncated. The division operation is performed on selected dividend and divisor bits using the proposed approximate subtractor. The same methodology was applied to produce a 2k-bit SQR circuit within a 2n-bit framework, utilizing the proposed subtractor design intended for the 2k-bit SQR circuit. This adaptive operation results in minimal maximum error distances for the approximate divider/SQR circuit. Compared to existing divider circuits, the proposed approximate design, which uses 6-bit radicand, consumes up to 50% less power than SEERAD with level 3. In comparison to existing SQR circuits, the proposed approximate design, which uses 6-bit radicand, consumes up to 12.83% less power. Furthermore, the proposed designs demonstrate superior performance to other approximate designs in image processing applications.