Design of a Calibration Circuit for Adaptive Phase- Locked Loop in the 5GHz Range Using CMOS 180nm Technology

In this article, we present the design of a phase-locked loop (PLL) incorporating a digitally controlled calibration oscillator circuit for frequency adaptation. The adaptation process is carried out digitally, guided by the performance of the oscillator. When the oscillator experiences a deviation from its specified frequency range, the active calibration circuitry detects the lock state and applies an appropriate digital code to the capacitor bank. This eliminates the need for user intervention to reprogram the PLL for frequency adjustment. The proposed circuit comprises a voltage-controlled oscillator (VCO) equipped with a capacitor bank and a digital calibration circuit, allowing for a broader range of output frequencies to be covered. The designed PLL circuit operates effectively within the frequency range of 3 to 6.7GHz, utilizing CMOS $180 \mathrm{~nm}$ technology with $1.8 \mathrm{~V}$ supply voltage and $15.5 \mathrm{~mW}$ power consumption, and has undergone rigorous simulation. The design successfully achieves a 200MHz frequency range variation for the reference frequency, with a phase noise value of $-122.71 \mathrm{dBc} / \mathrm{Hz}$ at 10MHz. The innovation in this paper lies in the capability of the proposed design for tracking the reference frequency. In the event of a change in the reference frequency, there is no need for user intervention to reprogram the phase-locked loop (PLL). The system automatically performs the relocking operation. This feature can be utilized in unmanned aerial vehicles (UAVs or drones) to implement frequency hopping capabilities.