Lint, CDC and RDC analysis for PCIe subsystem using VC_Spyglass

this project focuses on addressing critical Lint, CDC, and RDC challenges in chip design Where different parts of the system operate on signals with varying clock frequencies. To ensure the proper synchronization and handling of these signals and mitigate potential timing violations and functional failures, Lint, CDC, and RDC analyses are done. Spyglass is a widely used tool for carrying out this analysis. The study involves a comprehensive analysis, debugging, and modification of design related to missing or incorrect declarations, uninitialized variables, unreachable code, and coding guideline violations. Additionally, the project extensively examines CDC issues, such as metastability and data corruption risks, and leverages Spyglass to identify problems like inadequate synchronization techniques, missing synchronization paths, and violations of CDC guidelines. SoC designs have a variety of reset sources, including hardware resets, software resets, watchdog timer resets, debug resets, and power-on resets.