Implementation of 1-bit Full Adder using Various Low Power Techniques on 45nm Technology

Full Adder is the most commonly used digital component, with applications in arithmetic implementations, processors, digital filters, etc. It plays a critical role in determining the overall power of a digital system, so the reduction in power for this component can reduce the power of the overall system drastically. This paper implements and compares various low-power techniques suggested for a 1-bit full adder. These techniques usually revolve around logic style, hybrid digital styles, redundant components, and reduced transistor count techniques. In this paper, three types of techniques are discussed. The Gate-diffused Input (GDI) technique aims to lower the voltage swing for power reduction [1]. Using redundant components like multiplexers can comparatively reduce power, and decrease the circuit complexity [2]. Mixing of different techniques is also possible, this can be seen in hybrid module implementation [3]. All these different techniques are implemented at 45nm process node, in Cadence Virtuoso. The results for the same were analyzed, tabulated, and compared. Further, a layout for a 16T hybrid full adder was prepared after which post-layout simulations were performed and the results were compared. Monte Carlo analysis was also performed for observing the average power consumption in 16T hybrid full adder.