gm/Id Methodology Based Programmable LDO Design Process

The purpose of this paper is to outline a structured procedure for designing a programmable LDO using $\frac{{{g_m}}}{{{I_d}}}$ methodology in 90nm technology. The dimensions of the MOSFETs, bias voltages, and other parameters will be determined from the graphical plots produced using the said methodology. A control unit will be designed to generate eight unique reference voltages using 3-bit input. The Constructed LDO will generate the appropriate output voltages from 1V to 1.7V based on the reference voltages. The validity of the design will be verified by simulating the corner analysis and Monte Carlo in Cadence’s Spectre.