A Satisfibility based Watermarking Approach for Hardware Security in High Level Synthesis

In today’s world Time-To-Market (TTM) plays a very important role in the success of any given chip. To reduce the TTM, many manufacturers rely on reusable IP cores. These reusable Intellectual Property(IP) cores may come with a lot of unforeseen security issues related to reliability and verifiable point of origin. This paper presents a way of watermarking to reduce these security threats by embedding the designer’s watermark into an IP design at High Level Synthesis (HLS) stage. A boolean Satisfibility (SAT) based approach is proposed which has no additional area and performance overhead.