Efficient weight-based segmentation of scan-chains using NLFSR

This paper presents an efficient Built-in self-test (BIST) module using a Non-Linear Feedback Shift Register (NLFSR) and Weight based segmentation of scan-chains. The proposed technique reduces the test application time and consumption of power of the BIST module by segmenting the scan-chain into multiple scan-chains by grouping the cells of the scan chain having similar weights (logic 1's and 0's). Every scan- chain thus grouped will be given test patterns through the combinational circuit. Pseudo-random Number Generator (PRNG) generates test patterns for testing the circuit under test (CUT). By using NLFSR as PRNG the power consumption is reduced. The weight calculations and NLFSR are simulated and synthesized using Xilinx Vivado. Experiments are carried over on the ISCAS89 benchmark circuits on the Fsim tool.