A 25 – 50 GHz Inductor-Less Divide-by-4 with Microstrip Line Connection in 40 nm CMOS

This paper reports on a current-mode logic based master slave D flip-flop inductor-less divide-by-4 frequency divider that operates up to 50 GHz. By using a microstrip line structure for the signal lines and symmetrical arrangement of the master latch and slave latch DFFs, the parasitic inductance and capacitance due to the signal lines are reduced and high frequency operation is achieved without peaking inductors. The divider is designed using a 40 nm bulk CMOS process, and we show that the proposed technique can realize a divider with a core area of 0.0455 mm
²
that operates in the frequency range of 25 – 50 GHz without any bias adjustment.