A L/S/C/X/Ku-Band Three-Stack, Two stages Fully Integrated CMOS Power Amplifier with 20.9 % PAE Using T-Network

This work proposes an L/S/C/X/Ku-Band three-stack two stages fully integrated CMOS power amplifier (PA) that realized in 65nm and achieves high efficiency, high output power over wide impedance bandwidth from 2-20 GHz. The proposed PA circuit comprises of T-network broadband input power match design, interstage tuning network and output power stage. The interstage tuning network is employed to achieve an excellent gain ($\left|\mathrm{S}_{21}\right|$) flatness of 16.3 ± 0.9 dB. The proposed PA design is employed 3-stack of transistor under supply of 3V at stage-1 followed LC and stage-2 to achieve high output power. The load pull analysis is performed to optimize the T- type output matching network for achieving PAE of 20.9 % and output power of 15.97 dBm at 7 GHz with $50 \Omega$ load impedance. Besides, this PA provides 1 dB output compression point of 11.2 ± 0.8 dBm over full frequency band and also achieves the output third order intercept point of 23.2 dBm at 7 GHz using two tone signal.