Low Phase Noise DDS-Driven PLL Frequency Synthesizer for Joint Communication and Sensing Applications

A low phase noise (PN) direct digital synthesizer (DDS)-driven phase-locked loop (PLL) frequency synthesizer is designed and implemented for joint communication and sensing (JCS) applications. The DDS, which generates the reference signal for the integer-N PLL, allows the synthesizer to provide fast frequency ramp signal for the frequency-modulated continuous wave (FMCW) radar mode and frequency-switchable low spurious and PN local oscillator (LO) signal for the communication mode. The PLL is designed based on an offset mixing architecture, which reduces the feedback frequency division ratio in the loop, to generate the low PN signal for the JCS systems. A low PN step recovery diode (SRD)-based high-order frequency multiplication chain is employed to serve as both the reference clock for the DDS and the LO of the mixer to reduce PN, power consumption, volume and cost. The implemented frequency synthesizer exhibits an excellent PN better than −120.1 dBc/Hz at 10 kHz offset from 4.6 to 5.4 GHz.