Flexible MEMS-IC Microsystem by a Wafer-Level F-eSiFO Integration Process

This paper reports a novel F-eSiFO fabrication strategy of flexible microsystems based on the mature eSiFO (Embedded Silicon Fan-Out) technology. Heterogeneous dielets were embedded onto a silicon interposer and flexibly interconnected by the Parylene-MEMS process. The electrical wiring between different dielets realized ultra-fine line width and ultra-small pitches (L/S≤2μm). The F-eSiFO prepared high-density flexible microsystem presented stretchability at 33.3% ± 4.41% and Si areal coverage at 76%. The micro-Kirigami structures were fabricated, enhancing the stretchability to 50.7%± 3.71%. The F-eSiFO prepared flexible microsystem has shown great potential in MEMS-IC wafer-level manufacturing and packaging with the excellent electrical conduction capability to conform to complex and dynamic surfaces, which shows a promising future for more applications in flexible microsystems.