Behavioral Modeling of A High-Resolution Sigma-Delta Analog-to-Digital Converter

A 24-bit high-resolution sigma-delta analog-to-digital converter (ADC) with 4
^th
-order, 3-bit quantization, and cascaded integrators feed-forward (CIFF) topology is presented in this paper. The ADC is simulated in Simulink with non-ideal factors such as clock jitter, thermal noise, op-amp noise, and non-ideal integrators are analyzed and modeled. The simulation shows that the signal-to-noise ratio (SNR) of the non-ideal model is 136.6 dB and the effective number of bits (ENOB) is 22.73 bits. The sigma-delta ADC satisfies the requirements of high-precision conversion in a variety of industrial measurement scenarios (such as detection and navigation, biosensing, etc.) and medical treatment.