Design and Analysis of Pruned Approximate Majority Logic Based Adder

Approximate computing acts as a new concept for nanoscale technologies, which helps to reduce power without giving accurate results. Fundamentally important 3input majority voter, MV of Majority logic (ML)) is utilized in new nanotechnologies. MV has been widely used in digital circuit design. To achieve performance and accuracy tradeoffs, this work employs pruning technique in the design of ML adders. Time consumption, gates requirement and error analysis are used to investigate the proposed design. Xilinx ISE 14.7 software is employed to verify the functionality and to analyse the hardware performance metrics of the proposed circuit design and Python Jupyter Notebook is used to find error metrics.